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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8074/ad8075 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. www.analog.com 500 mhz, g = +1 and +2 triple video buffers with disable functional block diagram oe dgnd in2 agnd in1 agnd in0 v ee v cc v cc out2 v ee out1 v cc out0 v ee ad8074 /ad8075 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 g = +1/+2 g = +1/+2 g = +1/+2 features dual supply 5 v high-speed fully buffered inputs and outputs 600 mhz bandwidth (C3 db) 200 mv p-p 500 mhz bandwidth (C3 db) 2 v p-p 1600 v/ s slew rate, g = +1 1350 v/ s slew rate, g = +2 fast settling time: 4 ns low supply current: <30 ma excellent video specifications (r l = 150 ): gain flatness of 0.1 db to 50 mhz 0.01% differential gain error 0.01 differential phase error all hostile crosstalk C80 db @ 10 mhz C50 db @ 100 mhz high off isolation of 90 db @ 10 mhz low cost fast output disable feature applications rgb buffer in lcd and plasma displays rgb driver video routers product description the ad8074/ad8075 are high-speed triple video buffers with g = +1 and +2 respectively. they have a ? db full signal band- width in excess of 450 mhz, along with slew rates in excess of 1400 v/ s. with better than ?0 db of all hostile crosstalk and 90 db isolation, they are useful in m any high-speed applica- tions. the differential gain and differential phase error are 0.01% and 0.01 . gain flatness of 0.1 db up to 50 mhz makes the ad8074/ad8075 ideal for rgb buffering or driving. they consume less than 30 ma on a 5 v supply. both devices offer a high-speed disable feature that allows the outputs to be put into a high impedance state. this allows the building of larger input arrays while minimizing ?ff?chan- nel output loading. the ad8074/ad8075 are offered in a 16-lead tssop package. table i. truth table oe out0, 1, 2 0 in0, in1, in2 1 high z rev. b
C2C ad8074/ad8075?pecifications (t a = 25 c, v s = 5 v, unless otherwise noted.) parameter conditions min typ max unit dynamic performance ? db bandwidth (small signal) v in = 200 mv p-p, c l = 5 pf 330/310 600/550 mhz v in = 200 mv p-p, r l = 150 ? 250/230 400/400 mhz ? db bandwidth (large signal) v in = 2 v p-p, c l = 5 pf 330/300 500/500 mhz v in = 2 v p-p, r l = 150 ? 250/230 350/350 mhz 0.1 db bandwidth v in = 200 mv p-p, c l = 5 pf 70/65 mhz v in = 200 mv p-p, r l = 150 ? 70/65 mhz slew rate 2 v step, r l = 1 k ? /150 ? 1600/1350 v/ s settling time to 0.1% 2 v step, r l = 1 k ? /150 ? 4/7.5 ns noise/distortion performance differential gain v = 3.58 mhz, 150 ? 0.01 % differential phase v = 3.58 mhz, 150 ? 0.01 degrees all hostile crosstalk v = 10 mhz, r l = 1 k ? ?0/?4 db v = 100 mhz, r l = 1 k ? ?0/?4 db off isolation v = 10 mhz, r l = 150 ? 90 db voltage noise v = 10 khz to 100 mhz 19.5/22 nv/ hz dc performance voltage gain error no load 0.1/ 0.2 0.15/ 0.65 % input offset voltage 2.5 27/40 mv t min to t max 3m v input offset drift 10 v/ c input bias current 5 9.5/10 a input characteristics input resistance 10 m ? input capacitance channel enabled 1.5 pf channel disabled 1.5 pf input voltage range 2.8/ 1.4 v output characteristics output voltage swing r l = 1 k ? +v s ?1.95 +v s ?1.8 v ? s + 2.1 ? s + 1.8 v r l = 150 ? +v s ?2.35 +v s ?2.2 v ? s + 2.30 ? s + 2.2 v short circuit current (protected) 70 ma output resistance enabled 0.5 ? disabled 3.5 7.5 m ? output capacitance disabled 2.2 pf power supply operating range 4.5 5.5 v power supply rejection ratio +psrr: +v s = +4.5 v to +5.5 v, ? s = ? v 60 74 db psrr: ? s = ?.5 v to ?.5 v, +v s = +5 v 56 64 db quiescent current all channels ?n 21.5/24 30 ma all channels ?ff 3/4 5.5 ma t min to t max 23/26 ma digital input logic ??voltage oe input 2.0 v logic ??voltage oe input 0.8 v logic ??input current oe = 4 v 100 na logic ??input current oe = 0.4 v 1 a operating temperature range temperature range operating (still air) ?0 +85 c ja operating (still air) 150.4 c/w jc operating 27.6 c/w specifications subject to change without notice. rev. b
ad8074/ad8075 C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 v internal power dissipation 2, 3 ad8074/ad8075 16-lead tssop (ru) . . . . . . . . . . . . . 1 w input voltage in0, in1, in2 . . . . . . . . . . . . . . . . . . . . . . . . . v ee v in v cc oe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd v in v cc output short circuit duration . . . . . . . . . . . . . . . . . . indefinite 3 storage temperature range . . . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air (t a = 25 c). 3 16-lead plastic tssop; ja = 150.4 c/w. maximum internal power dissipa- tion (p d ) should be derated for ambient temperature (t a ) such that p d < (150 c ?t a )/ ja . pin configuration oe dgnd in2 agnd in1 agnd in0 v ee v cc v cc out2 v ee out1 v cc out0 v ee ad8074 /ad8075 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 g = +1/+2 g = +1/+2 g = +1/+2 maximum power dissipation the maximum power that can be safely dissipated by the ad8074/ ad8075 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junc- tion temperature of 175 c for an extended period can result in device failure. while the ad 8074/ad8075 is internally short circuit pr otected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 1. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8074/ad8075 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ambient temperature ? c maximum power dissipation ?watts t j = 150 c 010 30 50 70 90 0 0.5 1.0 1.5 ?0 ?0 ?0 figure 1. maximum power dissipation vs. temperature rev. b
ad8074/ad8075 typical performance characteristics C4C gain 2v p-p 200mv p-p frequency mhz gain db 0.1 1000 1 10 100 1 0 1 2 3 4 5 6 7 8 9 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 flatness db flatness tpc 1. ad8074 frequency response; r l = 150 ? gain db 0.1 1000 1 10 100 2 1 0 1 2 3 4 5 6 7 8 9 10 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 flatness db 200mv p-p 2v p-p gain flatness frequency mhz 200mv p-p 2v p-p tpc 2. ad8074 frequency response; r l = 1 k ? , c l = 5 pf gain db 3 2 1 0 1 2 3 4 5 6 7 8 9 10 0.1 1 10 100 1000 frequency mhz v out = 2v p-p c l = 10pf c l = 0pf c l = 5pf v in v out c l 1k 75 tpc 3. ad8074 frequency response vs. capacitive load flatness gain 2v p-p 200mv p-p 2v p-p frequency mhz 0.1 1000 1 10 100 1 0 1 2 3 4 5 6 7 8 9 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 normalized flatness db normalized gain db tpc 4. ad8075 frequency response; r l = 150 ? 0.1 1000 1 10 100 2 1 0 1 2 3 4 5 6 7 8 9 10 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 2v p-p gain flatness normalized flatness db normalized gain db 200mv p-p frequency mhz 2v p-p tpc 5. ad8075 frequency response; r l = 1 k ? , c l = 5 pf normalized gain db 3 2 1 0 1 2 3 4 5 6 7 8 9 10 0.1 1 10 100 1000 frequency mhz v out = 2v p-p c l = 10pf c l = 0pf c l = 5pf v in v out c l 150k 75 tpc 6. ad8075 frequency response vs. capacitive load rev. b
ad8074/ad8075 C5C frequency mhz 0 0.1 1000 1 10 100 10 20 30 40 50 60 70 80 90 100 110 v out = 2v p-p (active channel(s)) r l = 1k r t = 37.5 all-hostile adjacent crosstalk db tpc 7. ad8074 crosstalk vs. frequency (all hostile and adjacent r l = 1 k ? ) fundamental frequency mhz 0 1 1000 10 100 10 20 30 40 50 60 70 80 90 100 v out = 2v p-p r l = 150 r t = 37.5 third harmonic second harmonic distortion dbc tpc 8. ad8074 distortion vs. frequency frequency mhz 0 0.1 1000 1 10 100 10 20 30 40 50 60 70 80 90 100 110 v out = 2v p-p (active channel(s)) r l = 150 r t = 37.5 all-hostile adjacent crosstalk db tpc 9. ad8075 crosstalk vs. frequency (all hostile and adjacent r l = 150 ? ) fundamental frequency mhz 0 1 1000 10 100 10 20 30 40 50 60 70 80 90 100 second harmonic third harmonic v out = 2v p-p r l = 150 r t = 37.5 distortion dbc tpc 10. ad8075 distortion vs. frequency rev. b
ad8074/ad8075 C6C frequency mhz 0.1 1000 1 10 100 20 30 40 50 60 70 80 90 100 110 r l = 1k r l = 150 off isolation db tpc 11. ad8074 off isolation vs. frequency frequency mhz 0.1 1000 1 10 100 20 30 40 50 60 70 80 10 0 10 +psrr psrr psrr db tpc 12. ad8074 psrr vs. frequency voltage noise nv/ hz 10 100 1m 1k 10k 100k frequency hz 350 300 250 200 150 100 50 0 tpc 13. ad8074 voltage noise vs. frequency frequency mhz 0.1 1000 1 10 100 20 30 40 50 60 70 80 90 100 110 r l = 1k r l = 150 off isolation db tpc 14. ad8075 off isolation vs. frequency frequency mhz 0.1 1000 1 10 100 10 20 30 40 50 60 70 20 10 0 +psrr psrr psrr db tpc 15. ad8075 psrr vs. frequency 10 100 1m 1k 10k 100k voltage noise nv/ hz frequency hz 350 300 250 200 150 100 50 0 400 tpc 16. ad8075 voltage noise vs. frequency rev. b
ad8074/ad8075 C7C frequency mhz 0.1 1000 1 10 100 10000 1000 100 10 1 0.1 0.01 input impedance k tpc 17. ad8074 input impedance vs. frequency frequency mhz 0.1 1000 1 10 100 1000 100 10 1 0.1 output impedance tpc 18. ad8074 output impedance vs. frequency; enabled frequency mhz 0.1 1000 1 10 100 0.001 1000 100 10 1 0.1 0.01 output impedance k tpc 19. ad8074 output impedance vs. frequency; disabled frequency mhz 0.1 1000 1 10 100 10000 1000 100 10 1 0.1 0.01 input impedance k tpc 20. ad8075 input impedance vs. frequency frequency mhz 0.1 1000 1 10 100 1000 100 10 1 0.1 output impedance tpc 21. ad8075 output impedance vs. frequency; enabled frequency mhz 0.1 1000 1 10 100 0.001 1000 100 10 1 0.1 0.01 output impedance k tpc 22. ad8075 output impedance vs. frequency; disabled rev. b
ad8074/ad8075 C8C 2ns v o = 200mv step 0 0.15 0.10 0.05 0.05 0.10 0.15 tpc 23. ad8074 small signal pulse response (r l = 1 k ? , c l = 5 pf) 0 0.2 0.1 0.6 0.1 0.2 0.3 0.4 0.5 0.7 0.8 2ns v o = 700mv step tpc 24. ad8074 video amplitude pulse response (r l = 1 k ? , c l = 5 pf) 0 1.5 1.0 1.5 0.5 1.0 0.5 2ns v o = 2v step tpc 25. ad8074 large signal pulse response (r l = 1 k ? , c l = 5 pf) 0 0.15 0.10 0.15 0.05 0.10 0.05 2ns v o = 200mv step tpc 26. ad8075 small signal pulse response (r l = 150 k ? ) 2ns 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v o = 700mv step tpc 27. ad8075 video amplitude pulse response (r l = 150 ? ) 1.5 0 0.5 1.0 1.5 1.0 0.5 2ns v o = 2v step tpc 28. ad8075 large signal pulse response (r l = 150 ? ) rev. b
ad8074/ad8075 C9C theory of operation the ad8074 (g = +1) and ad8075 (g = +2) are triple-channel, high-speed buffers with ttl-compatible output enable control. optimized for buffering rgb (red, green, blue) video sources, the devices have high peak slew rates, maintaining their band- width for large signals. additionally, the buffers are compensated for high phase margin, minimizing overshoot for good pixel resolution. the buffers also have video specifications that are suitable for buffering ntsc or pal composite signals. the buffers are organized as three independent channels, each with an input transconductance stage and an output trans- impedance stage. each channel is characterized by low input capacitance and high input impedance. the transconductance stages, npn differential pairs, source signal current into the folded cascode output stages. each output stage contains a compensat- ing network and emitter follower output buffer. internal voltage feedback sets the gain, the ad8074 being configured as a unity gain follower, and the ad8075 as a gain-of-two amplifier with a feedback network. the architecture provides drive for a reverse- terminated video load (150 ? ) with low differential gain and phase error for relatively low power consumption. careful chip design and layout allow excellent crosstalk isolation between channels. one logic pin, oe , controls whether the three outputs are enabled, or disabled to a high-impedance state. the high imped- ance disable allows larger matrices to be built when busing the outputs together. when disabled, the ad8074 and ad8075 con- sume a fifth the power as when enabled. in the case of the ad8075 (g = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. full power bandwidth for an undistorted sinusoid is often calcu- lated using peak slew rate from the equation: full power bandwidth peak slew rate sinusoidal amplitude = 2 peak slew rate is not the same as average slew rate (25% to 75%) which is typically specified. for a natural response, peak slew rate may be 2.7 times larger than average slew rate. there- fore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. the primary cause of overshoot in these amplifiers is the pres- ence of large reactive loads at the output and insufficient series isolation of the load. however, it is possible to overdrive these amplifi ers with 1 v, subnanosecond input-pulse edges. the ensuing dynamics may give rise to subnanosecond overshoot. to reduce these effects, an edge-rate limiting network at the input should be considered for input transition times less than 0.5 ns. applications response tuning it has been mentioned in passing that the primary cause of over- shoot for the ad8074 and ad8075 is the presence of large reactive loads at the output. if the system exhibits excessive ringing while settling, a 10 ? 50 ? series resistor may be used at the output to isolate the emitter-follower output buffer from the reactive load. if the output exhibits an overdamped response, the system designer may add a few pf shunt capacitance at the output to tune for a faster edge transition. a system with a small degree of overshoot will settle faster than an overdamped system. v in v out r s c l 1k 75 2ns r s = 0 c l = 5pf r s = 10 c l = 10pf r s = 20 c l = 15pf 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 figure 2. driving capacitive loads single supply operation the ad8074 and ad8075 may be operated from a single 10 v supply. in this configuration, the ad8075 s agnd pins must be tied near midsupply, as agnd provides the reference for the ground buffer, to which the internal gain network is terminated. logic is referenced to dgnd. the buffers are disabled in s ingle supply operation for v oe > v dgnd + ~2.0 v and enabled for v oe < v dgnd + 0.8 v. ttl logic levels are expected. the fol- lowing restrictions are placed upon the digital ground potential: 35 12 . vv v v avcc dgnd ? v dgnd v avee the architecture of the output buffer is such that the output voltage can swing to within ~2.3 v of either rail. for example, if the output need swing only 2 v, then the buffers could be oper- ated on dual 3.5 v or single 7 v supplies. it is cautioned that saturation effects may become noticeable when the output swings within 2.6 v of either rail. the system designer may opt to use this characteristic to his or her advantage by using the soft-saturation regime, (2.2 v 2.6 v from the supply rails), to tame excessive overshoot. the designer is cautioned that a charge storage associated time delay of several nanoseconds is incurred when recovering from soft-saturation. this effect results in longer settling tails. rev. b
ad8074/ad8075 C10C rgb buffer for second monitor the rgb signals for pc monitors are driven through coax cables whose characteristic impedance is 75 ? . the graphics chip will generally have current-source output drivers that should be double terminated with a 75 ? shunt termination at each end. on the transmit end, the shunt terminations are provided to ground close to the graphics ic, while the monitor terminates its end via internal termination resistors. while this scheme works well and is virtually foolproof for a single monitor, it leaves no means for passively connecting a second monitor to the same source. a second monitor that is connected simply in parallel will pro- vide an extra set of terminations that will upset the signal levels. to keep costs low, most computer monitors do not have the ability to open-circuit the terminations in order that an additional monitor can be connected to the same signal, as is done in some studio- type tv monitors. a way around this problem is to connect the first monitor to the rgb channels in the standard fashion, and then to provide a triple gain-of-two buffer to drive the second monitor. the ad8075 is designed to provide this function and also provide excellent high-frequency performance for high-resolution graphics signals. figure 3 shows a schematic of this circuit. the outputs of the ad8075 are low impedance voltage sources and are therefore series-terminated with 75 ? resistors. the internal resistors in monitor #2 provide the terminations at its end. the overall effect of this type of termination scheme is to divide the signal amplitude by two. this is compensated by the gain of two provided by the ad8075. 0.1f 5v 0.1f 5v 0.1f 5v + 25f 0.1f +5v 0.1f +5v 0.1f +5v + 25f ad8075 75 75 75 75 75 75 75 75 75 monitor #1 monitor #2 internal terminations internal terminations 75 75 75 r g b pc graphics ic current source output drivers figure 3. buffer rev. b
ad8074/ad8075 C11C triple video multiplexer the ad8074 and ad8075 each have an output-enable function that can be used to disable the outputs and put them in a high- impedance state. usually, for a unity-gain device, it is relatively easy to provide high disabled impedance, because the feedback path is from the output to a high-impedance input. however, for a non-unity-gain part, the feedback provides a resistive path to ground. t his will usually dominate the disabled output imped- ance, and make it a much lower value than the unity-gain device. the ad8075 has an internal buffer that provides a low-impedance, ground level output that terminates the feedback path d uring enabled operation. in the disabled state, both this buffer output and the amplifier output are disabled to a high impedance to provide a high-impedance disabled state. to construct a multiplexer, the outputs from one or more devices are connected in parallel and only one device is enabled at a time while all of the others are disabled. the two sets of inputs are applied individually to each of the separate device inputs. figure 4 shows the circuit details for this function. the first rgb source 1 is input to the first ad8075. each of the individual signals is terminated to ground with 75 ? to provide proper termination for the input cables. in a similar fashion, the source 2 signals are input to the second ad8075. 0.1f 5v 0.1f 5v 0.1f 5v + 25f 0.1f +5v 0.1f +5v 0.1f +5v + 25f ad8075 75 75 75 oe 75 75 75 r g b source 2 0.1f 5v 0.1f 5v 0.1f 5v + 25f 0.1f +5v 0.1f +5v 0.1f +5v + 25f ad8075 75 75 75 oe 75 75 75 r g b source 1 sel1/sel2 r g b output figure 4. mux rev. b
ad8074/ad8075 C12C each of the six outputs has a 75 ? series resistor that is used to reverse-terminate the output transmission line. the correspond- ing outputs are then wired in parallel and delivered to the output cable. the termination resistors in this position help to isolate the off capacitance of the disabled device s outputs from loading the enabled device s outputs. the gain-of-two of the ad8075 compensates for the signal halving that occurs as a result of the output terminations. a select signal is provided directly to the oe of the second ad8075 and an inverted version is used to drive the other device s oe . this will ensure that only one device is active at a time. since there is a total of 150 ? in series between any two outputs, it is not essential to be overly concerned about the exact tim ing of the making and breaking of the enable signals. additional inputs can easily be added to the circuit shown to make wider multiplexers. the outputs of all of the devices will be wired in parallel, and the logic must allow that only one output be enabled at a time. if it is desired to make a triple 3:1 multiplexer, a triple 2:1 mul- tiplexer, like the ad8185 can be used along with the ad8075. the same general guidelines for input and output treatment should be followed and the logic must perform the proper function. if it is desired to design such a multiplexer at unity gain, the ad8074 should be used. for a triple 3:1 multiplexer, an ad8183 (triple 2:1 mux) can be combined with an ad8074 to provide this function. layout and grounding the ad8074 and ad8075 are extreme bandwidth, high-slew-rate devices that are designed to drive up to the highest resolution monitors and provide excellent resolution. to realize their full performance potential, it is essential to adhere to the best prac- tices of high-speed pcb layout. a major area of focus should be the power distribution system. there should be a full ground plane that provides the reference and return paths for both the inputs and outputs. the ground also provides isolation between the input signals to minimize the crosstalk. this ground plane should cover as wide an area as possible and be minimally interrupted in order to keep its impedance to a minimum. the power planes should also be as broad as possible to provide minimal inductance, which is required for high-slew-rate sig- nals. these power planes layers should be spaced closely to the ground plane to increase the interplane capacitance between the supplies and ground. each supply pin should be bypassed with a low inductance 0.1 f ceramic capacitance with minimal excess circuit length to minimize the series impedance. a 25 f tantalum elec tro- lytic capacitor will supply a charge reservoir for lower frequency, high-amplitude transitions. the input and output signals should be run as directly as pos- sible in order to minimize the effects of parasitics. if they must run over a longer distance of more than a few centimeters, con- trolled impedance pcb traces should be used to minimize the effect of reflections due to mismatches in impedance and the proper termination should be provided. to avoid excess crosstalk, the above recommendations should be followed carefully. the power system and signal routing are the most important aspects of preventing excess crosstalk. beyond these techniques, shielding can be provided by ground traces between adjacent signals, especially those that travel parallel over long distances. rev. b
ad8074/ad8075 C13C agnd agnd tp4 tp3 do not install agnd agnd agnd do not install 10f c2 c1 10f 50 impedance line 50 impedance line v ee v ee v cc v cc agnd v ee v cc tp1 agnd tp2 agnd do not install agnd 75 impedance line 75 in1 in1 agnd r2 75 impedance line in2 75 r1 in2 agnd agnd agnd 75 impedance line in0 r3 75 in0 agnd 50 impedance line disout v cc w2 do not install r16 20k r11 50 c8 c6 disout tp5 v ee 0.01f 0.1f c3 v ee 0.1f agnd agnd c11 0.01f c7 0.1f agnd agnd out0 75 impedance line 75 r12 150 agnd do not install out0 r9 agnd agnd v ee out1 out2 v cc agnd 0.01f c13 c12 0.01f 75 impedance line agnd 75 impedance line r7 75 75 r8 150 r6 agnd r10 150 agnd do not install do not install out2 out1 agnd agnd agnd agnd v cc 0.01f c15 0.01f c14 v ee v cc v cc out2 v ee out1 v cc out0 v ee in0 agnd in1 agnd in2 dgnd oe ad8074 dut + + 3 p1 1 p1 2 p1 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 figure 5. evaluation board schematic rev. b
ad8074/ad8075 C14C figure 6. component side figure 7. circuit side figure 8. silkscreen top figure 9. silkscreen bottom figure 10. internal 2 rev. b
ad8074/ad8075 rev. b outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 1. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8074aru ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad8074aruz ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad8074aruz-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad8074aruz-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 AD8075ARUZ ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 AD8075ARUZ-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 AD8075ARUZ-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 ad8074z-eval evaluation board ad8075z-eval evaluation board 1 z = rohs compliant part. revision history 10/11rev. a to rev. b changes to ordering guide ........................................................... 15 10/01rev. 0 to rev. a changes to single-supply operation section ................................ 9 ?2001C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02391-0-10/11(b)

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